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49ad084503
Bug #79636: CACHE_LINE_SIZE should be 128 on AArch64 Bug #79637: Hard-coded cache line size Bug #79638: Reconcile CACHE_LINE_SIZE with CPU_LEVEL1_DCACHE_LINESIZE Bug #79652: Suspicious padding in srv_conc_t - changed CPU_LEVEL1_DCACHE_LINESIZE to default to 128 bytes on POWER and AArch64 architectures in cases when no value could be detected by CMake using getconf - changed CACHE_LINE_SIZE definition in ut0counter.h to be an alias of CPU_LEVEL1_DCACHE_LINESIZE - changed a number of hard-coded 64-byte cache line size values in the InnoDB code - fixed insufficient padding for srv_conc members in srv0conc.cc Ported to Mariadb by Daniel Black <daniel.black@au.ibm.com> Added s390 cache size of 256 at same time.
26 lines
980 B
CMake
26 lines
980 B
CMake
# Copyright (c) 2009, 2011, 2012 Oracle and/or its affiliates. All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Symbols with information about the CPU.
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FIND_PROGRAM(GETCONF getconf)
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MARK_AS_ADVANCED(GETCONF)
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IF(GETCONF)
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EXECUTE_PROCESS(
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COMMAND ${GETCONF} LEVEL1_DCACHE_LINESIZE
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OUTPUT_VARIABLE CPU_LEVEL1_DCACHE_LINESIZE
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)
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ENDIF()
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