mirror of
https://github.com/MariaDB/server.git
synced 2025-01-20 05:52:27 +01:00
284 lines
6.9 KiB
C++
284 lines
6.9 KiB
C++
/* Copyright (C) 2003 MySQL AB
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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#ifndef NDB_INTERPRETER_HPP
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#define NDB_INTERPRETER_HPP
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#include <ndb_types.h>
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class Interpreter {
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public:
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inline static Uint32 mod4(Uint32 len){
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return len + ((4 - (len & 3)) & 3);
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}
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/**
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* General Mnemonic format
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*
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* i = Instruction - 5 Bits ( 0 - 5 ) max 63
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* x = Register 1 - 3 Bits ( 6 - 8 ) max 7
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* y = Register 2 - 3 Bits ( 9 -11 ) max 7
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* b = Branch offset (only branches)
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*
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* 1111111111222222222233
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* 01234567890123456789012345678901
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* iiiiiixxxyyy bbbbbbbbbbbbbbbb
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*
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*
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*/
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/**
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* Instructions
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*/
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static const Uint32 READ_ATTR_INTO_REG = 1;
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static const Uint32 WRITE_ATTR_FROM_REG = 2;
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static const Uint32 LOAD_CONST_NULL = 3;
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static const Uint32 LOAD_CONST16 = 4;
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static const Uint32 LOAD_CONST32 = 5;
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static const Uint32 LOAD_CONST64 = 6;
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static const Uint32 ADD_REG_REG = 7;
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static const Uint32 SUB_REG_REG = 8;
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static const Uint32 BRANCH = 9;
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static const Uint32 BRANCH_REG_EQ_NULL = 10;
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static const Uint32 BRANCH_REG_NE_NULL = 11;
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static const Uint32 BRANCH_EQ_REG_REG = 12;
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static const Uint32 BRANCH_NE_REG_REG = 13;
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static const Uint32 BRANCH_LT_REG_REG = 14;
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static const Uint32 BRANCH_LE_REG_REG = 15;
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static const Uint32 BRANCH_GT_REG_REG = 16;
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static const Uint32 BRANCH_GE_REG_REG = 17;
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static const Uint32 EXIT_OK = 18;
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static const Uint32 EXIT_REFUSE = 19;
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static const Uint32 CALL = 20;
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static const Uint32 RETURN = 21;
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static const Uint32 EXIT_OK_LAST = 22;
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static const Uint32 BRANCH_ATTR_OP_ARG = 23;
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static const Uint32 BRANCH_ATTR_EQ_NULL = 24;
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static const Uint32 BRANCH_ATTR_NE_NULL = 25;
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/**
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* Macros for creating code
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*/
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static Uint32 Read(Uint32 AttrId, Uint32 Register);
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static Uint32 Write(Uint32 AttrId, Uint32 Register);
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static Uint32 LoadNull(Uint32 Register);
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static Uint32 LoadConst16(Uint32 Register, Uint32 Value);
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static Uint32 LoadConst32(Uint32 Register); // Value in next word
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static Uint32 LoadConst64(Uint32 Register); // Value in next 2 words
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static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
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static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
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static Uint32 Branch(Uint32 Inst, Uint32 R1, Uint32 R2);
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static Uint32 ExitOK();
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/**
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* Branch string
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*
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* i = Instruction - 5 Bits ( 0 - 5 ) max 63
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* a = Attribute id
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* l = Length of string
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* b = Branch offset
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* t = branch type
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* d = Array length diff
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* v = Varchar flag
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* p = No-blank-padding flag for char compare
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*
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* 1111111111222222222233
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* 01234567890123456789012345678901
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* iiiiii ddvtttpbbbbbbbbbbbbbbbb
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* aaaaaaaaaaaaaaaallllllllllllllll
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* -string.... -
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*/
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enum UnaryCondition {
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IS_NULL = 0,
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IS_NOT_NULL = 1
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};
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enum BinaryCondition {
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EQ = 0,
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NE = 1,
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LT = 2,
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LE = 3,
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GT = 4,
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GE = 5,
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LIKE = 6,
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NOT_LIKE = 7
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};
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static Uint32 BranchCol(BinaryCondition cond,
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Uint32 arrayLengthDiff, Uint32 varchar, bool nopad);
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static Uint32 BranchCol_2(Uint32 AttrId);
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static Uint32 BranchCol_2(Uint32 AttrId, Uint32 Len);
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static Uint32 getBinaryCondition(Uint32 op1);
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static Uint32 getArrayLengthDiff(Uint32 op1);
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static Uint32 isVarchar(Uint32 op1);
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static Uint32 isNopad(Uint32 op1);
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static Uint32 getBranchCol_AttrId(Uint32 op2);
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static Uint32 getBranchCol_Len(Uint32 op2);
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/**
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* Macros for decoding code
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*/
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static Uint32 getOpCode(Uint32 op);
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static Uint32 getReg1(Uint32 op);
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static Uint32 getReg2(Uint32 op);
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static Uint32 getReg3(Uint32 op);
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};
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inline
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Uint32
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Interpreter::Read(Uint32 AttrId, Uint32 Register){
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return (AttrId << 16) + (Register << 6) + READ_ATTR_INTO_REG;
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}
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inline
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Uint32
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Interpreter::Write(Uint32 AttrId, Uint32 Register){
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return (AttrId << 16) + (Register << 6) + WRITE_ATTR_FROM_REG;
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}
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inline
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Uint32
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Interpreter::LoadConst16(Uint32 Register, Uint32 Value){
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return (Value << 16) + (Register << 6) + LOAD_CONST16;
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}
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inline
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Uint32
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Interpreter::LoadConst32(Uint32 Register){
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return (Register << 6) + LOAD_CONST32;
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}
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inline
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Uint32
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Interpreter::LoadConst64(Uint32 Register){
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return (Register << 6) + LOAD_CONST64;
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}
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inline
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Uint32
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Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){
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return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG;
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}
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inline
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Uint32
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Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){
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return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG;
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}
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inline
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Uint32
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Interpreter::Branch(Uint32 Inst, Uint32 R1, Uint32 R2){
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return (R1 << 9) + (R2 << 6) + Inst;
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}
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inline
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Uint32
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Interpreter::BranchCol(BinaryCondition cond,
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Uint32 arrayLengthDiff,
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Uint32 varchar, bool nopad){
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//ndbout_c("BranchCol: cond=%d diff=%u varchar=%u nopad=%d",
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//cond, arrayLengthDiff, varchar, nopad);
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return
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BRANCH_ATTR_OP_ARG +
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(arrayLengthDiff << 9) +
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(varchar << 11) +
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(cond << 12) +
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(nopad << 15);
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}
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inline
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Uint32
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Interpreter::BranchCol_2(Uint32 AttrId, Uint32 Len){
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return (AttrId << 16) + Len;
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}
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inline
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Uint32
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Interpreter::BranchCol_2(Uint32 AttrId){
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return (AttrId << 16);
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}
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inline
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Uint32
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Interpreter::getBinaryCondition(Uint32 op){
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return (op >> 12) & 0x7;
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}
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inline
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Uint32
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Interpreter::getArrayLengthDiff(Uint32 op){
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return (op >> 9) & 0x3;
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}
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inline
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Uint32
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Interpreter::isVarchar(Uint32 op){
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return (op >> 11) & 1;
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}
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inline
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Uint32
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Interpreter::isNopad(Uint32 op){
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return (op >> 15) & 1;
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}
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inline
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Uint32
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Interpreter::getBranchCol_AttrId(Uint32 op){
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return (op >> 16) & 0xFFFF;
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}
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inline
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Uint32
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Interpreter::getBranchCol_Len(Uint32 op){
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return op & 0xFFFF;
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}
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inline
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Uint32
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Interpreter::ExitOK(){
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return EXIT_OK;
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}
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inline
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Uint32
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Interpreter::getOpCode(Uint32 op){
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return op & 0x3f;
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}
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inline
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Uint32
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Interpreter::getReg1(Uint32 op){
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return (op >> 6) & 0x7;
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}
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inline
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Uint32
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Interpreter::getReg2(Uint32 op){
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return (op >> 9) & 0x7;
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}
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inline
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Uint32
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Interpreter::getReg3(Uint32 op){
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return (op >> 16) & 0x7;
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}
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#endif
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