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The problem was due to a misuse of GCC asm constraints used to implement a atomic load. On x86_64, the load was implemented as a cmpxchg which implicitly uses the eax register as a source and destination operand, yet the dummy value used for comparison wasn't being properly loaded into eax (and other problems). The core problem is that cmpxchg is unnecessary as a load on x86_64 as there are other simpler instructions such as xadd. Even though, such instructions are only used to have a memory barrier as load and stores are atomic by definition. Hence, the solution is to explicitly issue the required CPU and compiler barriers. include/atomic/x86-gcc.h: Issue a synchronizing instruction before loading the value. Afterwards, issue a compiler barrier to prevent reordering. |
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| .. | ||
| gcc_builtins.h | ||
| generic-msvc.h | ||
| nolock.h | ||
| rwlock.h | ||
| solaris.h | ||
| x86-gcc.h | ||