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This is an addendum to the fix for MDEV-7026. The ARM memory model is similar to that of PowerPC and thus needs the same semantics with respect to memory barriers. That is, os_atomic_test_and_set_*_release() must be a store with a release barrier followed by a full barrier. Unlike x86 using __sync_lock_test_and_set() which is implemented as “exclusive load with acquire barriers + exclusive store” is insufficient in contexts where os_atomic_test_and_set_*_release() macros are used. |
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