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79 lines
3 KiB
C
79 lines
3 KiB
C
/* Copyright (c) 2019, 2020, MariaDB Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
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#include <my_global.h>
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#include <my_cpu.h>
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#include <my_rdtsc.h>
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#ifdef HAVE_PAUSE_INSTRUCTION
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/** How many times to invoke PAUSE in a loop */
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unsigned my_cpu_relax_multiplier = 200;
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#define PAUSE4 MY_RELAX_CPU(); MY_RELAX_CPU(); MY_RELAX_CPU(); MY_RELAX_CPU()
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#define PAUSE16 PAUSE4; PAUSE4; PAUSE4; PAUSE4
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/**
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Initialize my_cpu_relax_multiplier.
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Determine the duration of a PAUSE instruction by running an
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unrolled loop of 16 PAUSE instructions twice, and taking the
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faster of the two runs. In this way, even if the execution is
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interrupted by the operating system, it should be extremely
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unlikely that both loops get interrupted.
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On the Intel Skylake microarchitecture, the PAUSE instruction takes
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around 140 clock cycles, while on earlier microarchitectures it could
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be 10 clock cycles or less. Scale the PAUSE loop counter accordingly.
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On a pre-Skylake Intel Xeon CPU E5-2630 v4 @ 2.20GHz running an AMD64
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executable, the numbers would be between 172 and 220 when all the code
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is inlined as follows:
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rdtsc,mov,shl,or, 16*pause,
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rdtsc,mov,shl,or, 16*pause,
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rdtsc.
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That would yield 11 to 14 cycles per PAUSE instruction even if we
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(wrongly) ignore the overhead of the other instructions.
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On a Skylake mobile processor Intel Core i7-6500U CPU @ 2.50GHz, the
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numbers would range from 1896 to 2410 (or 1976 if taking the minimum
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of two runs), yielding 118 to 151 (or 123) cycles per PAUSE instruction.
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Let us define a threshold at roughly 30 cycles per PAUSE instruction,
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and use a shorter delay if the PAUSE instruction takes longer than
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that. In some AMD processors, the PAUSE instruction could take 40 or
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50 cycles. Let us use a shorter delay multiplier for them as well.
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The 1/2 scaling factor (200/100) was derived experimentally by
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Steve Shaw from Intel and Sergey Vojtovich from MariaDB Foundation.
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In an earlier experiment on MySQL code base, a 1/10 scaling factor
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(200/20) seemed to work best.
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The basic idea of the detection algorithm (run 16 PAUSE instructions
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between RDTSC) was suggested by Mikhail Sinyavin from Intel.
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*/
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void my_cpu_init(void)
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{
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ulonglong t0, t1, t2;
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t0= my_timer_cycles();
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PAUSE16;
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t1= my_timer_cycles();
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PAUSE16;
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t2= my_timer_cycles();
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if (t2 - t1 > 30 * 16 && t1 - t0 > 30 * 16)
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my_cpu_relax_multiplier= 100;
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}
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#endif
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