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MDEV-9872: Generic CRC32 message using ptr

Browse source 
Signed-off-by: Daniel Black <daniel.black@au.ibm.com>
This commit is contained in:
Daniel Black 2016-12-01 12:35:59 +11:00
parent 3d0d290fde
commit ba6af68c0f
6 changed files with 19 additions and 35 deletions
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4
storage/innobase/include/ut0crc32.h
View file

@ -54,8 +54,6 @@ extern ut_crc32_func_t ut_crc32_legacy_big_endian;
but very slow). */
extern ut_crc32_func_t ut_crc32_byte_by_byte;
/** Flag that tells whether the CPU supports CRC32 or not */
extern bool ut_crc32_sse2_enabled;
extern bool ut_crc32_power8_enabled;
extern const char *ut_crc32_implementation;
#endif /* ut0crc32_h */

9
storage/innobase/srv/srv0start.cc
View file

@ -1702,13 +1702,8 @@ innobase_start_or_create_for_mysql(void)
srv_boot();
if (ut_crc32_sse2_enabled) {
ib::info() << "Using SSE crc32 instructions";
} else if (ut_crc32_power8_enabled) {
ib::info() << "Using POWER8 crc32 instructions";
} else {
ib::info() << "Using generic crc32 instructions";
}
ib::info() << ut_crc32_implementation;
if (!srv_read_only_mode) {

18
storage/innobase/ut/ut0crc32.cc
View file

@ -96,6 +96,9 @@ ut_crc32_func_t ut_crc32_legacy_big_endian;
but very slow). */
ut_crc32_func_t ut_crc32_byte_by_byte;
/** Text description of CRC32 implementation */
const char *ut_crc32_implementation = NULL;
/** Swap the byte order of an 8 byte integer.
@param[in] i 8-byte integer
@return 8-byte integer */
@ -116,10 +119,6 @@ ut_crc32_swap_byteorder(
/* CRC32 hardware implementation. */
/* Flag that tells whether the CPU supports CRC32 or not */
bool ut_crc32_sse2_enabled = false;
UNIV_INTERN bool ut_crc32_power8_enabled = false;
#ifdef HAVE_CRC32_VPMSUM
extern "C" {
unsigned int crc32c_vpmsum(unsigned int crc, const unsigned char *p, unsigned long len);
@ -284,8 +283,6 @@ ut_crc32_hw(
{
uint32_t crc = 0xFFFFFFFFU;
ut_a(ut_crc32_sse2_enabled);
/* Calculate byte-by-byte up to an 8-byte aligned address. After
this consume the input 8-bytes at a time. */
while (len > 0 && (reinterpret_cast<uintptr_t>(buf) & 7) != 0) {
@ -375,8 +372,6 @@ ut_crc32_legacy_big_endian_hw(
{
uint32_t crc = 0xFFFFFFFFU;
ut_a(ut_crc32_sse2_enabled);
/* Calculate byte-by-byte up to an 8-byte aligned address. After
this consume the input 8-bytes at a time. */
while (len > 0 && (reinterpret_cast<uintptr_t>(buf) & 7) != 0) {
@ -427,8 +422,6 @@ ut_crc32_byte_by_byte_hw(
{
uint32_t crc = 0xFFFFFFFFU;
ut_a(ut_crc32_sse2_enabled);
while (len > 0) {
ut_crc32_8_hw(&crc, &buf, &len);
}
@ -706,6 +699,8 @@ void
ut_crc32_init()
/*===========*/
{
bool ut_crc32_sse2_enabled = false;
bool ut_crc32_power8_enabled = false;
#if defined(__GNUC__) && defined(__x86_64__)
uint32_t vend[3];
uint32_t model;
@ -741,6 +736,7 @@ ut_crc32_init()
ut_crc32 = ut_crc32_hw;
ut_crc32_legacy_big_endian = ut_crc32_legacy_big_endian_hw;
ut_crc32_byte_by_byte = ut_crc32_byte_by_byte_hw;
ut_crc32_implementation = "Using SSE2 crc32 instructions";
}
#endif /* defined(__GNUC__) && defined(__x86_64__) */
@ -748,6 +744,7 @@ ut_crc32_init()
#ifdef HAVE_CRC32_VPMSUM
ut_crc32_power8_enabled = true;
ut_crc32 = ut_crc32_power8;
ut_crc32_implementation = "Using POWER8 crc32 instructions";
#endif
if (!ut_crc32_sse2_enabled && !ut_crc32_power8_enabled) {
@ -755,5 +752,6 @@ ut_crc32_init()
ut_crc32 = ut_crc32_sw;
ut_crc32_legacy_big_endian = ut_crc32_legacy_big_endian_sw;
ut_crc32_byte_by_byte = ut_crc32_byte_by_byte_sw;
ut_crc32_implementation = "Using generic crc32 instructions";
}
}

3
storage/xtradb/include/ut0crc32.h
View file

@ -46,7 +46,6 @@ typedef ib_uint32_t (*ib_ut_crc32_t)(const byte* ptr, ulint len);
extern ib_ut_crc32_t ut_crc32;
extern bool ut_crc32_sse2_enabled;
extern bool ut_crc32_power8_enabled;
extern const char *ut_crc32_implementation;
#endif /* ut0crc32_h */

8
storage/xtradb/srv/srv0start.cc
View file

@ -1938,13 +1938,7 @@ innobase_start_or_create_for_mysql(void)
srv_boot();
if (ut_crc32_sse2_enabled) {
ib_logf(IB_LOG_LEVEL_INFO, "Using SSE crc32 instructions");
} else if (ut_crc32_power8_enabled) {
ib_logf(IB_LOG_LEVEL_INFO, "Using POWER8 crc32 instructions");
} else {
ib_logf(IB_LOG_LEVEL_INFO, "Using generic crc32 instructions");
}
ib_logf(IB_LOG_LEVEL_INFO, ut_crc32_implementation);
if (!srv_read_only_mode) {

12
storage/xtradb/ut/ut0crc32.cc
View file

@ -97,9 +97,8 @@ have support for it */
static ib_uint32_t ut_crc32_slice8_table[8][256];
static ibool ut_crc32_slice8_table_initialized = FALSE;
/* Flag that tells whether the CPU supports CRC32 or not */
UNIV_INTERN bool ut_crc32_sse2_enabled = false;
UNIV_INTERN bool ut_crc32_power8_enabled = false;
/** Text description of CRC32 implementation */
const char *ut_crc32_implementation = NULL;
/********************************************************************//**
Initializes the table that is used to generate the CRC32 if the CPU does
@ -213,8 +212,6 @@ ut_crc32_sse42(
#if defined(__GNUC__) && defined(__x86_64__)
ib_uint64_t crc = (ib_uint32_t) (-1);
ut_a(ut_crc32_sse2_enabled);
while (len && ((ulint) buf & 7)) {
ut_crc32_sse42_byte;
}
@ -302,6 +299,7 @@ void
ut_crc32_init()
/*===========*/
{
bool ut_crc32_sse2_enabled = false;
#if defined(__GNUC__) && defined(__x86_64__)
ib_uint32_t vend[3];
ib_uint32_t model;
@ -336,14 +334,16 @@ ut_crc32_init()
#endif /* defined(__GNUC__) && defined(__x86_64__) */
#ifdef HAVE_CRC32_VPMSUM
ut_crc32_power8_enabled = true;
ut_crc32 = ut_crc32_power8;
ut_crc32_implementation = "Using POWER8 crc32 instructions";
#else
if (ut_crc32_sse2_enabled) {
ut_crc32 = ut_crc32_sse42;
ut_crc32_implementation = "Using SSE2 crc32 instructions";
} else {
ut_crc32_slice8_table_init();
ut_crc32 = ut_crc32_slice8;
ut_crc32_implementation = "Using generic crc32 instructions";
}
#endif
}