From 720a0f6c78655e9cb29bc4fff4e4aac7e962a7aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marko=20M=C3=A4kel=C3=A4?= <marko.makela@mariadb.com>
Date: Wed, 24 Apr 2024 12:39:30 +0300
Subject: [PATCH] MDEV-33447 fixup for POWER 8

pmem_phwsync(): The implementation for POWER ISA v3.1 that is
compatible with libpmem.

pmem_fence(): A dummy implementation for older ISA. While such systems
are unlikely to support MAP_SYNC memory mappings, this could be useful
when running tests with memory-mapped /dev/shm/*/ib_logfile0
(the "fake PMEM"), to ensure that mariadb-backup will be able to
read the latest redo log contents.

pmem_persist_init(): Check the availability of POWER ISA v3.1.
Thanks to Daniel Black for suggesting this.
---
 storage/innobase/include/cache.h |  2 +-
 storage/innobase/sync/cache.cc   | 41 +++++++++++++++++++++++++-------
 2 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/storage/innobase/include/cache.h b/storage/innobase/include/cache.h
index 770f4d96477..0647cbe6dc4 100644
--- a/storage/innobase/include/cache.h
+++ b/storage/innobase/include/cache.h
@@ -19,7 +19,7 @@ this program; if not, write to the Free Software Foundation, Inc.,
 #pragma once
 #include <cstddef>
 
-#if defined __x86_64__ || defined __aarch64__
+#if defined __x86_64__ || defined __aarch64__ || defined __powerpc64__
 struct pmem_control
 {
   void (*persist)(const void *, size_t);
diff --git a/storage/innobase/sync/cache.cc b/storage/innobase/sync/cache.cc
index 6d3d5b4c4ac..43d642d05b5 100644
--- a/storage/innobase/sync/cache.cc
+++ b/storage/innobase/sync/cache.cc
@@ -24,7 +24,7 @@ last revised in libpmem-1.12.0. */
 #include "cache.h"
 #include <cstdint>
 
-#if defined __x86_64__ || defined __aarch64__
+#if defined __x86_64__ || defined __aarch64__ || defined __powerpc64__
 # ifdef __x86_64__
 static void pmem_clflush(const void *buf, size_t size)
 {
@@ -96,14 +96,9 @@ static decltype(pmem_control::persist) pmem_persist_init()
 {
   return (getauxval(AT_HWCAP) & HWCAP_DCPOP) ? pmem_cvap : pmem_cvac;
 }
-# endif
-
-pmem_control::pmem_control() : persist(pmem_persist_init()) {}
-const pmem_control pmem;
-#else
-void pmem_persist(const void *buf, size_t size)
+# elif defined __powerpc64__
+static void pmem_phwsync(const void* buf, size_t size)
 {
-# ifdef __powerpc64__
   for (uintptr_t u= uintptr_t(buf) & ~(CPU_LEVEL1_DCACHE_LINESIZE),
          end= uintptr_t(buf) + size;
        u < end; u+= CPU_LEVEL1_DCACHE_LINESIZE)
@@ -126,7 +121,35 @@ void pmem_persist(const void *buf, size_t size)
 #  else
   __asm__ __volatile__(".long 0x7c80040a" ::: "memory");
 #  endif
-# elif defined __riscv && __riscv_xlen == 64
+}
+
+#  include <atomic>
+static void pmem_fence(const void*, size_t)
+{
+  std::atomic_thread_fence(std::memory_order_seq_cst);
+}
+
+#  include <sys/auxv.h>
+#  ifndef AT_HWCAP2
+#   define AT_HWCAP2 26
+#  endif
+#  ifndef PPC_FEATURE2_ARCH_3_1
+#   define PPC_FEATURE2_ARCH_3_1 4
+#  endif
+
+static decltype(pmem_control::persist) pmem_persist_init()
+{
+  return (getauxval(AT_HWCAP2) & PPC_FEATURE2_ARCH_3_1)
+    ? pmem_phwsync : pmem_fence;
+}
+# endif
+
+pmem_control::pmem_control() : persist(pmem_persist_init()) {}
+const pmem_control pmem;
+#else
+void pmem_persist(const void *buf, size_t size)
+{
+# if defined __riscv && __riscv_xlen == 64
   __asm__ __volatile__("fence w,w" ::: "memory");
 # elif defined __loongarch64
   __asm__ __volatile__("dbar 0" ::: "memory");